17th
Apr
FET (Field Effect Transistors) MCQ

FET (Field Effect Transistors) MCQ

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  • 17th Apr, 2021
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FET (Field Effect Transistors) MCQ Test

Following are mostly asked Fet (field effect transistors) MCQ test that are designed for professionals like you to crack you interviews. You can take this Fet (field effect transistors) online test before appearing to you real interview. This Fet (field effect transistors) quiz there are around 30+ multiple choice questions on Fet (field effect transistors) with four options.

1) The two important advantages of a JFET are …………..

  • A. low input impedance and high output impedance
  • B. high input impedance and square-law property
  • C. inexpensive and high output impedance
  • D. none of the above

2) …………. has the lowest noise-level.

  • A. JFET
  • B. tetrode
  • C. triode
  • D. ordinary trnsistor

3) A MOSFET uses the electric field of a ………. to control the channel current

  • A. generator
  • B. capacitor
  • C. battery
  • D. none of the above

4) Which of the following devices has the highest input impedance?

  • A. ordinary transistor
  • B. Crystal diode
  • C. MOSFET
  • D. JFET

5) In class A operation, the input circuit of a JFET is ………. biased

  • A. reverse
  • B. forward
  • C. not
  • D. none of the above

6) The gate voltage in a JFET at which drain current becomes zero is called ……….. voltage.

  • A. active
  • B. cut-off
  • C. pinch-off
  • D. saturation

7) The channel of a JFET is between the …………….

  • A. input and output
  • B. gate and source
  • C. drain and source
  • D. gate and drain

8) The constant-current region of a JFET lies between...............

  • A. o and IDSS
  • B. cut off and pinch-off
  • C. cut off and saturation
  • D. pinch-off and breakdown

9) A “U” shaped, opposite-polarity material built near a JFET-channel center is called the ……….

  • A. heat sink
  • B. drain
  • C. block
  • D. gate

10) A very simple bias for a D-MOSFET is called ……..

  • A. voltage-divider biasing
  • B. zero biasing
  • C. self biasing
  • D. gate biasing

11) When an input signal reduces the channel size, the process is called …….

  • A. gate charge
  • B. depletion
  • C. enhancement
  • D. substrate connecting

12) When applied input voltage varies the resistance of a channel, the result is called…………..

  • A. field effect
  • B. cutoff
  • C. polarization
  • D. saturization

13) The transconductance curve of a JFET is a graph of …………… vs ……….

  • A. ID × RDS
  • B. IS versus VDS
  • C. IC versus VCE
  • D. ID versus VGS

14) Which component is considered to be an “OFF” devic.

  • A. E-MOSFET
  • B. D-MOSFET
  • C. transistor
  • D. JFET

15) The common-source JFET amplifier has ………..

  • A. no voltage gain
  • B. a high input impedance and a voltage gain less than 1
  • C. a high input impedance and a very high voltage gain
  • D. a very high input impedance and a relatively low voltage gain

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